Differential capacitance is also referred to as electrode capacitance, which is a difference between the capacitances formed at two electrodes. Sensors working thereupon have been developed and extensively used for sensing capacitive variations caused by physical factors, such as pressures, acceleration, linear displacement and rotational angles. While the circuit layouts may vary with practical sensing requirements, such sensors generally produce the sensing value according to the difference between the individual capacitances of two electrodes therein.
U.S. Pat. No. 6,949,937 has proposed a sensing circuit as depicted in FIG. 1, which comprises a switched capacitor front-end 12 and an amplifier stage 14. A differential capacitance 10 is a capacitance between two electrodes and may be regarded as a combination of a pair of variable capacitors CT1 and CT2. The switched capacitor front-end 12 that includes a switching circuit 16 and a charge-storing circuit 18 is connected to the capacitors CT1 and CT2 at sensing terminals Input1 and Input2, respectively. By switching switches S1-S8 in the switching circuit 16, the capacitors CT1 and CT2 are connected to power sources VDD and VSS for supplying charges as desired. Then the charges of the capacitors CT1 and CT2 are repeatedly transferred to the capacitors C1 and C2 in the charge-storing circuit 18. Afterward, the charges of the capacitors C1 and C2 are stored into two terminals of a floating capacitor CD, so that the potential difference VCD between the two terminals of the capacitor CD corresponds to the difference between the capacitors CT1 and CT2. At last, the two terminals of the capacitor CD are connected to the inputs of the amplifier 14, so that the amplifier stage 14 amplifies and then outputs the potential difference VCD, thereby accomplishing measurement of the differential capacitance 10. FIGS. 2A-2E illustrate operation of the switched capacitor front-end 12 of FIG. 1. The known technique repeats the operation as shown in FIGS. 2A-2D in an over-sampling manner without resetting switches SR1 and SR2, thereby repeatedly charging and discharging the capacitors CT1 and CT2, and repeatedly transferring the charges to the individual storing capacitor C1 or C2 inside the charge-storing circuit 18, so as to collect charge averages within the switched capacitor front-end 12 and in turn suppress RF interference or source noises. Afterward, as shown in FIG. 2E, the charges of the capacitors C1 and C2 are stored to the two terminals of the capacitor CD, and then amplified and output by the amplifier stage 14 that is at the back-end part of FIG. 1 and connected to the two terminals of the capacitor CD. Since the known technique collects charge averages by repeatedly operating only the switched capacitor front-end 12 in the front-end part for averaging instead of repeatedly operating the entire circuit, it helps to reduce power loss.
However, such an existing approach is not effective enough in noise reduction. Taking the capacitor C1 for example, according to the law of charge conservation, the output voltage after n rounds of charge transfer is determined as
                                          V                          OUT              ⁢                                                          ⁢              1                                =                                    V              n                        +                                          V                                  n                  -                  1                                            ·              X                        +                                          V                                  n                  -                  2                                            ·                              X                2                                      +            Λ            +                                          V                1                            ·                              X                                  n                  -                  I                                                                    ,                            [                  Eq          ⁢                      -                    ⁢          1                ]                                          X          =                                    C              ⁢                                                          ⁢              1                                                      CT                ⁢                                                                  ⁢                1                            +                              CT                ⁢                                                                  ⁢                2                            +                              C                ⁢                                                                  ⁢                1                                                    ,                            [                  Eq          ⁢                      -                    ⁢          2                ]                                                      V                          i              ,                              i                =                                  1                  ⁢                                                                          ⁢                  …                  ⁢                                                                          ⁢                  n                                                              =                                    VDD              i                        ×                                          CT                ⁢                                                                  ⁢                1                                                              CT                  ⁢                                                                          ⁢                  1                                +                                  CT                  ⁢                                                                          ⁢                  2                                +                                  C                  ⁢                                                                          ⁢                  1                                                                    ,                            [                  Eq          ⁢                      -                    ⁢          3                ]            where X is typically between 0.1 and 0.5, and VDDi may be regarded as incorporating RF interference and source noises while the equivalent source VDD varies over time. According to the equations Eq-1, Eq-2 and Eq-3, after n rounds of sampling and transfer, all the results are affected by the factor X except for the result of the nth rounds. Since X<1, the earlier result affects the final output less. In other words, VOUT1 approximates Vn, so the over-sampling operation under this configuration fails to effectively average charges and reduce noises.
In addition, the amplifier stage 14 uses the operational amplifier to directly amplify the difference VCD between the corresponding output voltages VOUT1 and VOUT2, so the non-ideal effects of the operational amplifier (e.g. offsets, flicker noise and finite gain error) are output through the output terminal as well, making the sensing performance deteriorated.